Integrated circuit with diamond insulator

ABSTRACT

PCT No. PCT/US94/02569 Sec. 371 Date Dec. 4, 1995 Sec. 102(e) Date Dec. 4, 1995 PCT Filed Mar. 9, 1994 PCT Pub. No. WO94/20985 PCT Pub. Date Sep. 15, 1994A semiconductor-on-diamond structure has a free-standing layer of diamond material that is thick enough to provide integrity for the integrated circuit and to insulate the circuit. The structure has a layer of diamond material 12 on a layer of silicon nitride 62. A device layer of semiconductor material 30 is positioned over the silicon nitride layer.

FIELD OF THE INVENTION

The present invention relates to integrated electronic circuitryfabricated in semiconductor-on-insulator structures and, moreparticularly, to improved silicon-on-diamond circuits and methods offabricating such structures.

BACKGROUND AND SUMMARY OF THE INVENTION

It is known that diamond material possesses desirable mechanical,electrical and thermal properties for application to integratedcircuitry. WO 94/15359 published 7 Jul. 1994, "Silicon On DiamondCircuit Structure", assigned to the assignee of the present application,which discloses a method for forming an integrated circuit structurehaving a layer of crystalline silicon formed over a diamond layer. Amongother applications, such a structure is useful for providing heatdissipation paths of enhanced thermal conductivity. Resulting advantagesinclude increased power handling capability and higher levels of deviceintegration.

More generally, integrated circuits fabricated onsemiconductor-on-insulator (SOI) structures offer performance advantagesincluding freedom from latchup for CMOS circuits, low parasiticcapacitance, low power consumption, radiation hardness, high temperatureoperation, high voltage operation and the possibility of multi-layerdevice integration. Commonly, in SOI structures, device islands areformed by extending isolation trenches through the device semiconductorlayer down to an insulation level. Sidewalls for such trenches areformed with an insulator such as silicon dioxide.

Fabrication of silicon-on-diamond structures may begin with preparationof a wafer growth substrate for receiving a polycrystalline diamond filmthereover. After deposition of the diamond material, e.g., by PlasmaEnhanced Chemical Vapor Deposition (PECVD), a thin polycrystalline oramorphous silicon film is formed over the diamond layer, perhaps to athickness of less than one micron. Next, the silicon film is prepared toprovide a smooth bonding surface for receiving a second wafer. Thesecond wafer includes a semiconductor layer of suitable quality forformation of integrated circuit devices thereon. Further details aredisclosed in WO 94/15359 now incorporated herein by reference.Generally, the wafer substrate upon which the diamond film is grownbecomes an integral part of the SOI structure.

Other techniques for fabricating silicon on insulator devices usingbonded wafers with a diamond layer and a silicon dioxide or siliconnitride layer on the diamond layer are shown in Research Disclosure No.345, January 1993, page 76, Abstract No. 345114 and WO 91/11822.Techniques for oxide bonding and silicide bonding are described,respectively, in Japanese Journal of Applied Physics Vol. 30, No. 10A,Part 2, 10 Oct. 1991, pages L1693-L1695 and IEDM 1986, pages 210-213.Another technique shown in EP-A-0317124 forms a silicon on diamonddevice using traditional deposition and removal steps without bondingtwo wafers together.

For the above-referenced process, deposition conditions must becarefully chosen to assure adhesion of the diamond film to the wafersubstrate and to minimize warpage of the substrate once the diamonddeposition is complete. Subsequent processing to form integrated circuitdevices on the SOI structure has limited the choice of growth substratematerials to those compatible with the processing environment.

It is now recognized that the optimal film characteristics desired forapplication of diamond as a buried insulator in an SOI structure are notnecessarily consistent with the characteristics imposed by the growthsubstrate bonded thereto. For example, due to differences in materialsproperties, e.g., thermal expansion characteristics, thermal cycling maylimit the variety of wafer substrate types which are compatible with theformation of diamond layers.

To acquire improved characteristics there is now provided a method forpreparing a semiconductor-on-insulator structure beginning withprovision of a removable deposition surface and formation of diamondmaterial thereon. The resulting diamond layer includes first and secondopposing surfaces with the first surface initially in contact with thedeposition surface. The first surface of the diamond layer is separatedfrom the deposition surface. A bond is formed between one of the diamondsurfaces and a wafer structure comprising a layer of semiconductormaterial.

Structures and methods are also provided for protecting the integrity ofdiamond material during semiconductor processing and for preventingdiffusion of carbon from the diamond material into another layer of asemiconductor structure. Generally, an integrated circuit structurecomprises a layer of diamond, a layer of silicon nitride formed on thediamond and a layer of semiconductor material over the nitride layer.According to one embodiment of the invention, the structure may befabricated by first depositing a layer of diamond material and formingsilicon nitride over the layer. A layer or wafer of semiconductormaterial is bonded to the diamond layer with the nitride layerpositioned at the interface. Alternately, after depositing thediamond-containing layer and bonding a semiconductor layer to thediamond layer, trenches are formed through the semiconductor material tothe diamond layer and silicon nitride is deposited in the trenches.

BRIEF DESCRIPTION OF THE FIGURES

FIGS. 1A-1I illustrate fabrication of a silicon-on-diamond circuitstructure according to the invention;

FIG. 2 illustrates a growth substrate for receiving polycrystallinediamond material;

FIG. 3 illustrates silicon nitride layers formed on diamond material;

FIGS. 4A-4F provide, in sequence, partial views of a silicon-on-diamondstructure during device island formation;

FIGS. 5A-5G illustrate in partial view a method of incorporating siliconnitride on diamond material when forming device islands; and

FIGS. 6A-6D illustrate in partial view still another sequence forfabricating device islands.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1(A-F) illustrate one embodiment of the inventive concept.Initially a sacrificial substrate 10 of silicon carbide (SiC) isselected as a medium upon which a diamond film is grown. In thispreferred embodiment SiC is chosen for the growth substrate 10 becauseit exhibits thermal expansion characteristics relatively close to thoseof the diamond film to be grown thereover, thus reducing the likelihoodof incurring deleterious effects during temperature cycling. Havingselected a substrate with desired characteristics for thermal cyclingand for influencing both nucleation and surface growth, apolycrystalline diamond film is deposited on the substrate 10. The filmis grown to sufficient thickness to provide necessary integrity for afree-standing diamond wafer and to avoid warpage problems.

As illustrated in FIG. 1A a diamond layer 12 is deposited over a growthsurface 14 of the substrate 10. Deposition may be performed by HotFilament Chemical Vapor Deposition (HFCVD) at a substrate temperature inthe range of 700° to 1000° C. This results in a fairly uniformcomposition of polycrystalline diamond. Note, when the substrate surface14 is polished to a desired specification, the resulting diamond surface16 (see also FIG. 1B) formed against the substrate will exhibit asubstantially equivalent degree of planarity or flatness. Thus surface16 can provide a greater degree of uniformity and planarity than theopposing diamond surface 18 without grinding or polishing the diamondmaterial.

The composite structure is next subjected to an appropriate chemicalenvironment for removal of the substrate 10. For example, with a SiCsubstrate the free-standing diamond wafer of FIG. 1B is formed bydipping the structure in a bath of KOH heated to 60° C. to completelyremove the SiC.

The newly exposed diamond surface 16, formerly against the substratesurface 14, is of superior quality for subsequent wafer bonding.Alternately, as previously known, one would first planarize and thenbond the surface 18 in order to join the diamond layer 12 to adevice-quality layer. Here, in addition to providing the high qualitysurface 16, the opposing surface 18 of the now free-standing diamondlayer 12 may be polished to provide a desired overall uniformity inthickness and flatness. Of course this polishing could be performedprior to removal of the substrate 10. Such precision is desirable whenproviding a very thin semiconductor film over each of the surfaces 16and 18 in order to build submicron integrated circuit devices on bothsides of the insulative diamond layer 12.

Next an intermediate bonding layer is formed over the diamond surface16. For example, deposit approximately 500 Angstroms of polysilicon oramorphous silicon on the newly exposed smooth diamond surface 16 by lowpressure chemical vapor deposition (LPCVD) at a temperature in the rangeof 600° C. FIG. 1C illustrates the diamond layer of FIG. 1B invertedwith such a deposited silicon layer 20 formed thereover. Subsequently, asecond layer 22 of silicon film is deposited on the diamond surface 18.Formation of the second layer 22, although not essential, is desirable,among other reasons, to facilitate die attachment during laterprocessing. See FIG. 1D which illustrates a two micron thick polysiliconfilm deposited by LPCVD, again in the temperature range of 600° C., toprovide this die-attach layer 22. The resulting laminate structure 24can next be bonded to a layer of, or wafer comprising, device-qualitysemiconductor material.

The structure 24 is more versatile and functional than prior materialsand composites which have been bonded to device-quality semiconductorlayers. Formerly, device wafers were bonded to what was termed a"handle" wafer in order to assure mechanical integrity during subsequentthermal processing and wafer handling. In contrast, the laminatestructure 24 comprises a diamond layer which, in addition to protectingthe integrity of an adjoining device layer, provides high thermalconductivity and dielectric isolation in relation to subsequently formedelectronic devices. Moreover, the structure 24 may be formed in a mannerwhich influences the electrical characteristics of both the diamond andthe interfacial region between the diamond and the device layer.

FIG. 1E illustrates a bonded wafer 28 comprising a monocrystallinesilicon, device-quality wafer 30 attached through the intermediatesilicon layer 20 to the diamond layer 12. As used herein, the termmonocrystalline implies a lattice structure, with or without defects orimpurities. Bonding between the wafer 30 and the layer 20 should bepreceded by a prebond surface treatment consisting of for example, an N₂SO₄ /H₂ O₂ cleaning followed by a second cleaning with NH₄ OH and a spinrinse/dry. Enhanced bonding between the silicon layer 20 and the bondingsurface of the wafer 30 may be had by formation of oxide at theinterface 32. For example, inclusion of a liquid oxidant, such as water,in a high temperature anneal, e.g., above 900° C., in a neutral ambientor steam environment for several hours results in an oxygen bond betweenlattice silicon and polycrystalline silicon. For further details seeU.S. Pat. No. 4,962,062 issued Oct. 9, 1990, incorporated herein byreference. See, also, U.S. Pat. No. 5,334,273, assigned to the assigneeof the present invention, disclosing a preferred liquid oxidant forenhancing bonded wafer yield.

Generally, a drop of liquid oxidant such as water plus hydrogen peroxideis placed on one of the bonding surfaces. Next, the device wafer isplaced against the wafer structure 24. The drop of oxidant should have avolume in the range of 0.8 to 8 micro liters per square inch of wafersurface. Once the wafer 30 is positioned against the wafer structure 24,the contacting materials are allowed to dry for 24 to 48 hours. Next thecontacting wafers are reacted at 900° C. for two hours to formsilicon-oxygen bonds which fuse the wafers together. Once bonding iscomplete, the exposed surface 34 of the device wafer 30 may be cleanedand treated for further processing. Often it is desirable to thin thewafer 30 after bonding. It may also be desirable to initially implantthe wafer 30 with complementary dopants for subsequent formation of CMOScircuitry. The wafer 30 may further incorporate a higher quality crystalof desired purity by epitaxial growth over the surface 34. Subsequentlywell known processes may be followed to fabricate discrete devices orintegrated circuits in and over the device wafer layer. It is common toform dielectrically isolated device islands in the device-quality layer.

When processing is complete, the polysilicon layer 22 may be coated witha thermally grown oxide. This can be removed by a wet chemical etch witha buffered oxide etch or by a dry plasma etch with CF₄ or SF₆.Integrated circuits or discrete devices formed on the bonded wafer arethen separated into die by laser ablation or sawing. The exposedpolysilicon layer 22 is then solder attached to a copper heat sink asillustrated in FIG. 1F or eutectically attached to a gold plated packagecavity as illustrated in FIG. 1G. The polysilicon layer 22 could also beattached to a heat sink or package material with a silver-glass adhesivehaving high thermal conductivity characteristics.

For solder attachment as illustrated in FIG. 1F, an aluminum layer 40 isbonded to polysilicon layer 22. A titanium layer 42 is formed as adiffusion barrier between the aluminum and a nickel layer 44. The nickelis coated with a gold layer 46 to preserve the otherwise exposed bondingsurface from oxidation. To effect a bond between the Ni and the solderlayer 48, e.g., Pb/Sn, the gold diffuses into the adjoining materials.The solder effects attachment of the die to a copper heat sink 50. Theeutectic attachment of FIG. 1G is effected by placing a gold preform 52in contact with the polysilicon layer 22 and the gold plating 56 of apackage cavity. The system is heated at 425° C. to form a Au/Au bond.

Although conventional die attach techniques can be adapted to bond thepolysilicon layer 22 of FIG. 1E to a package, other approaches areavailable to attach the diamond layer 12. The bonded wafer 28 of FIG. 1Eneed not be formed with the polysilicon layer 22. Rather, a direct bondcould be formed between the diamond layer 12 and a nickel-plated packagecavity with a silver epoxy adhesive such as Dupont 5504 cured at 150° C.for 16 hours. Also, materials other than polysilicon could form anintermediate layer between the diamond and the die attach media.

An advantage of the invention is that a diamond layer in asemiconductor-on-insulator bonded wafer can be formed under growthconditions entirely independent from the influences or constraintsotherwise imposed by materials in the bonded wafer. For example, it isknown that crystalline defects (e.g., stacking faults, micro twins anddislocations) and other imperfections such as grain boundaries, surfaceroughness and impurities, all influence the resultant properties in aCVD diamond film. The processes of nucleation and surface growth ofdiamond material on non-diamond substrates influence crystalorientation, intrinsic stress and morphology of the deposited film. Thusmechanical, electrical and thermal properties, including conductivityand the coefficient of thermal expansion, are, in part, determined bythe choice of growth substrate. Specifically, transport behavior ofelectrons in the diamond film, e.g., in response to ionizing radiation,applied voltage or impurity diffusion, is significantly influenced-bythe composition and structure of the interfacial layer between thegrowth substrate and the overlying diamond film.

BONDING BY SILICIDE

FIGS. 1H-1I illustrate in cross sectional view a preferred silicidebonding method of forming a silicon-on-free-standing-diamond bondedwafer. The process begins with a 500 micron thick silicon device waferand a free standing diamond layer 12 of comparable diameter (asillustrated in FIG. 1E) having deposited polysilicon on both faces. Nextdeposit a 500 angstrom layer 24 of platinum or other refractory metal onthe smooth surface of polysilicon layer 20. See FIG. 1H.

Next, join the device silicon wafer 30 and the free standing diamondlayer 12 with the polysilicon and metal layers at the bonding interface.Heat the silicon-on-diamond structure to 500° C. in a 2-6 hour furnacecycle in an inert ambient such as nitrogen. This drives the metal toreact with the silicon from the device wafer and the polysilicon oflayer 20 to form silicide layer 26. This low temperature bonding resultsfrom a silicide reaction rather than thermal oxidation. See FIG. 1I.With platinum, silicon-platinum bonds form with silicon atoms from boththe device silicon wafer 30 and the polysilicon layer 20. The bondedzone will have a thickness of roughly 600 to 1000 Angstroms. Afterbonding, the bulk of the silicon device wafer can be removed bygrinding, lapping and polishing to leave the desired device siliconthickness. If other refractory metals such as tungsten and cobalt areused for the metal layer 24 instead of platinum, these may require ahigher anneal temperature for the silicide reaction.

The device silicon wafer may be replaced with a gallium arsenide waferfor mating with a free standing diamond film. The polysilicon andplatinum layers of the free standing diamond film are pressed against alayer, e.g., 500 Angstroms, of polysilicon deposited on the galliumarsenide wafer surface. A 500° C. two to six hour thermal cycle diffusesthe platinum into the polysilicon layer on the GaAs and the polysiliconlayer on the free standing diamond film. Again the bonding is dependentupon the silicidation reaction and not on oxidation. The advantage ofthe silicidation bonding with the GaAs to the free standing diamond filmis that it is a low temperature bonding process which will not cause theunwanted decomposition of either the diamond or the GaAs. Both materialsare stable well past 500° C.

In lieu of SiC a variety of materials may be selected for the growthsubstrate 10. Generally, once the diamond film is formed the growthsubstrate can be removed. For example, a tungsten substrate can beremoved with a 30% peroxide (H₂ O₂) solution by weight in water. Amolybdenum or copper substrate can be removed with a 50% water solutionof 70% mass concentration HNO₃ in water. Ni/Fe Alloy 42 can be removedby a 1:1 solution of Hcl (37% by mass) and HNO₃ (70% by mass). Kovar canbe removed in the same manner as Alloy 42 or by a 97% assay of hot H₂SO₄.

The growth substrate 10 may also be formed as a composite structure 58,indicated schematically in FIG. 2, comprising a relatively thick basesubstrate 60, e.g., 500 microns, with a thin film 62 formed thereover toprovide a growth surface 14 of choice. To prevent warpage of thesubstrate 60 due to differences in the coefficient of thermal expansion(CTE), a thin film 64 of like composition and thickness to film 62(e.g., 0.05-1.0 micron) may be formed on the opposing side of the basesubstrate 60. Table I lists a series of choices for the base substrate60 and thin film 62. Table I also indicates the CTE for the basesubstrate materials. Note, the CTE for polycrystalline diamond rangesfrom 2.0-2.3×E-6/C. For reasons now described, silicon nitride is anadvantageous growth substrate material.

                  TABLE I                                                         ______________________________________                                                     BASE SUBSTRATE CTE                                                                             THIN                                            BASE SUBSTRATES                                                                            (I E-6/°C.)                                                                             FILMS                                           ______________________________________                                        Si           2.3              Ti     Zr                                       Mo           5.0              Ta     Hf                                       W            4.5              Cu     Ni                                       Si.sub.3 N.sub.4                                                                           2.3              Mo     SiO.sub.2                                SiC          3.7              W      SiC                                                                    Pt     Si.sub.3 N.sub.4                                                       Nb                                              ______________________________________                                    

During the production and processing of SOI wafers, semiconductordevices are formed according to processes generally employing hightemperature ambient conditions. Diamond remains stable in an inertenvironment at temperatures near 1400° C. See J. E. Field, TheProperties of Diamonds, New York Academic Press 1979. Once adiamond-containing structure such as bonded wafer 28 is formed, it isdesirable to proceed with processing steps to form integrated circuitstructures including device islands. When processing involves removal ofwafer material such that the diamond layer becomes exposed, the processshould employ an environment which is inert with respect to the diamondsurface so that high-temperature conditions can be employed. This isbecause polycrystalline diamond becomes thermally unstable in an oxygenambient at temperatures near 700° C. See Ramesham, et al., J.Electrochem. Soc., Vol. 137, No. 10, October 1990, pages 3203-3205.

Although an inert atmosphere can preserve the integrity of the diamondat 700° C., such may not be suitable to a volume manufacturingenvironment, i.e., requiring a high degree of reliability, precision andrepeatability. Generally it is believed that the susceptibility ofdiamond integrity to a reactive environment will render standard, hightemperature, processes unsuitable. For example, silicon-based processingcommonly employs thermal oxidation of silicon at temperatures in excessof 700° C. in order to create a wide variety of oxides, e.g., fieldoxide, trench oxide, ion implantation mask oxide, gate oxide andcapacitor oxide. Such reactions would affect the diamond material.Alternatives such as oxide deposition are not desirable in volumemanufacture.

Furthermore, when diamond material is in direct contact withsemiconductor material such as silicon, there exists the possibility ofcarbon diffusion into the semiconductor. Diffusion resulting in carbonconcentrations on the order of 1E18 atoms per cm³ can cause formation ofmicrodefects and dislocations which will likely degrade minority carrierlifetime. See K. V. Ravi, Imperfections and Impurities in SemiconductorSilicon, Wiley: New York, 1981.

A method and structure are now described for protecting the integrity ofdiamond material during standard silicon processing, including oxideformation and deposition. An important feature associated with themethod and structure is the reduction of carbon migration into thesemiconductor material by an intervening dense material such as Si₃ N₄.

The structure of FIG. 3 may result by selection of silicon nitride asthe thin film 62 of a composite structure 58. For example, with alaminate arrangement such as described in FIG. 2, the diamond layer 12may be formed on surface 14 of a substrate 58 comprising two thin films62 and 64 of silicon nitride formed over opposing sides of a Mo basesubstrate 60. Before formation of an intermediate bonding layer, e.g.,like polysilicon layer 20, the Mo base substrate is removed with asolution of HNO₃ as previously described, leaving a thin film of siliconnitride denoted as layer 62 in FIG. 3. The silicon nitride layer 62serves as both an oxidative and a diffusion barrier to protect thediamond surface 16 during device formation. A second silicon nitridelayer 63 may be formed on the diamond surface 18 to provide an oxidativebarrier as well.

The choice of silicon nitride for the layer 62 is exemplary. Othermaterials may be suitable depending on the selection of materials forthe device wafer 30 as well as the specific process conditions.Generally, the layer 62 should comprise one or more materials whichprovide an effective barrier to oxidation and/or diffusion of oxygeninto the diamond. Note, unlike silicon dioxide, silicon nitride containsno oxygen which could migrate from the barrier layer itself into thediamond material.

A second desired feature is that the layer 62 should prevent diffusionof active dopant into the semiconductor material of the device wafer 30.Carbon acts as a dopant in silicon. Unlike silicon nitride, materialssuch as boron nitride and aluminum nitride-contain elements, e.g., boronand aluminum, which act as dopants in silicon. Thus, choice of materialfor the layer 62 is, in part, dependant on the choice of semiconductormaterial for the device wafer 30.

A silicon nitride barrier film can also be formed independent from thediamond growth process. Beginning with a free-standing diamond film 12such as previously described with reference to FIG. 1B, deposit the300-500 Angstrom layer 62 of silicon nitride on the smooth diamondsurface 16 (formerly bonded to a growth substrate) by reactingdichlorosilane with ammonia at 800° C. In addition, in lieu of apolysilicon layer 22 as illustrated in FIG. 1D, the second siliconnitride layer 63 may be deposited along the diamond layer surface 18.The polysilicon layer 22 (FIG. 1D) and the nitride layer 63 both providean oxidative barrier to protect the integrity of the diamond layer 12during thermal processing. Next, over the silicon nitride layer 62deposit an intermediate bonding layer 20, e.g., comprising approximately500 angstroms of polysilicon or amorphous silicon. The layer 20 can beformed by low pressure chemical vapor deposition at a temperature in therange of 600° C. See FIG. 3. The silicon nitride layer 62 provides bothan oxidative and diffusion barrier with respect to the overlyingpolysilicon layer 20 and a subsequently bonded device wafer 30 duringdevice formation. If nitride has not been deposited on the surface 18,deposit a two micron thick polysilicon layer.

Bonding with the device wafer 30 proceeds as previously described withreference to FIG. 1E to form a bonded wafer structure 65. For example,place a required number of drops of oxidizing liquid either with orwithout a dopant on the smooth, 500 angstrom polysilicon layer 20. Pressthe device wafer to the polysilicon surface containing the oxidizingliquid and thermally anneal this structure at 900° C. to produceoxidative bonding. Wafer processing may proceed as described elsewhereto complete an integrated circuit. See U.S. Pat. No. 5,362,667. Whenprocessing is complete, remove any grown oxides from the back surface ofthe diamond film. Wafers can then be laser ablated or sawn intoindividual die.

With a semiconductor-on-diamond bonded wafer structure, includingsilicon nitride layer 62 (but not necessarily layer 63), formation ofdevice islands may proceed as illustrated in FIGS. 4A-4F. For anexemplary bonded wafer structure 90 (FIG. 4A) lateral isolation beginswith formation of a thermal oxide 92 over a device silicon layer 94. Thesilicon layer 94 is bonded to a diamond substrate 96 through interveningsilicon nitride layer 98 (corresponding to layer 62 of FIG. 3) andthrough polysilicon layer 100 (corresponding to layer 20 of FIG. 3).Depending on the bonding reaction, a very thin (e.g., 10 to 30 Angstromssilicide or oxide) bond interface layer 102, will be present between thedevice silicon layer 94 and the diamond substrate 96. See U.S. Pat. No.5,387,555.

The SiO₂ layer 92 is patterned with an oxide etch, preferably a ReactiveIon Etch (RIE), forming vertical oxide sidewalls. Next, a dry etch isperformed in the device layer extending into the polysilicon layer 100.Removal of material in the device and polysilicon layers to form thetrench 104 is preferably accomplished with a two step etch. Abreakthrough isotropic plasma etch removes native oxide and carbonmatter. Next, the main etch, RIE, is anisotropic in nature. Etchconditions are summarized in Table 2.

                  TABLE 2                                                         ______________________________________                                                     STEP I        STEP II                                            DESCRIPTION  (BREAKTHROUGH)                                                                              (MAIN ETCH)                                        ______________________________________                                        HBR(sccm)    20            22                                                 SiF4(sccm)   --            5                                                  He/O.sub.2 (sccm)                                                                          --            8-12                                               NF.sub.3 (sccm)                                                                            5             --                                                 Pressure(mtorr)                                                                            20            100                                                B-Field(Gauss)                                                                             0             56                                                 Power(Watts) 450           400                                                time (sec)   60            800                                                ______________________________________                                    

If an oxide, rather than silicide, bond layer is present between thedevice silicon layer 94 and the nitride layer 98, the etch proceedsthrough the bond layer 102 to the silicon nitride layer 98. Alternately,if layer 102 is silicide, the etch may stop on the silicide. Silicideremoval can be effected by a 1:1 wet etch solution of HCl:HNO₃. Residualof layer 100 (polysilicon), if present, is removed by a dry etch (Table2 Step II). An HF dip will remove the masking oxide.

After formation of the trench 104, the oxide mask layer 92 is removed byan HF dip which further removes residual oxides. Next, silicon dioxidelayer 106 is formed along the trench walls, e.g., by plasma enhanced CVDof tetraethylorthosilicate (TEOS) at 400° C. The deposited SiO₂ isdensified at about 1000° C. in N₂.

After deposition of the SiO₂ by TEOS a thick, e.g., 2 micron,polysilicon layer 108 is deposited by LPCVD. Deposition thickness shouldbe adjusted to completely fill the trench as shown in FIG. 4C. The LPCVDpolysilicon is removed from the wafer surface by chemical/mechanicalpolishing. The polish stops on the densified SiO₂ layer 106. See FIG.4D. Next, polysilicon is removed from the trench 104 down to the uppersurface 103 of the device silicon layer 94 with a timed reactive ionetch (e.g., Step II of Table 2), or wet etchant (HNO₃ +HF). See FIG. 4E.Finally, the TEOS-deposited SiO₂ layer 106 remaining over the devicelayer 94 is removed with a plasma etch (e.g., see Step I of Table 2) toprovide the resulting structure of FIG. 4F.

As illustrated in FIG. 4F, the above-process is capable of providing acontinuous silicon nitride layer underlying both the trenches and theportions of the device silicon layer which become isolated deviceislands. Alternately, when the diamond substrate is bonded to the devicesilicon layer without an intervening nitride layer (e.g., with anintermediate polysilicon layer and either a bonding oxide or a bondingsilicide), it is desirable to protect diamond material which may beexposed to an oxidizing ambient during trench formation. FIG. 5Aillustrates such a bonded wafer 120 comprising a device silicon layer122 bonded to a diamond layer 124 by an intervening bonding layer 126comprising, for example, oxide or silicide. Trench formation begins withthermal growth of oxide on the silicon layer 122 followed by pattern andmask steps resulting in the masking oxide layer 128 (FIG. 5B). Next, anetch is performed such as described in Table 2. When the bonding layer126 is oxide the etch penetrates therethrough to stop on the diamondlayer 124. As discussed with reference to FIGS. 4 when the layer 126 issilicide, the RIE stops thereon (See FIG. 5C) and the silicide isremoved with a wet chemical etch to expose the diamond. An HF dip willalso remove the masking oxide. FIG. 5D illustrates the resulting trench129 after removal of both layer 126 and oxide mask 128.

Next, a 500 Angstrom layer 130 of silicon nitride is deposited in theresulting trench 129 and over the device silicon layer 122. The nitridelayer 130 is annealed at 800° C. to remove silicon defects and form athin oxide layer 134 along the nitride surface, e.g., less than 20angstroms as shown in FIG. 5B. The thin layer 134 provides a goodbonding surface for receiving deposited silicon dioxide or polysiliconduring subsequent trench refill steps. That is, TEOS SiO₂ and LPCVDpolysilicon are deposited to refill the trench as previously describedwith reference to FIG. 4C. See FIG. 5F which further illustrates theTEOS oxide layer 138 and the polysilicon fill layer 140. Withchemical/mechanical polishing the structure shown in FIG. 5G results.

As an alternate embodiment to the fabrication sequence of FIG. 5, thetrench formation of FIG. 5C, achieved with a dry etch, can be effectedwith a wet anisotropic etch in a KOH-n-propanol solution (85C). See FIG.6A which illustrates trenches 150 formed in the device monocrystallinesilicon layer 122 wherein the upper surface of the layer 122 is alongthe 1,0,0 lattice plane. The wet etch exposes trench walls 152 along the1,1,1 plane at a slope of 54.7 degrees relative to the 1,0,0 plane. Formany bipolar device applications a suitable thickness for the remainingisland portions of the device layer ranges from 10 to 20 microns. TheKOH etch will stop on the bonding layer 126. To expose the underlyingdiamond layer 124, removal of an oxide bonding layer is achieved with anHF wet etch while removal of a silicide bond can be had with aqua regia.See FIG. 6B. The process continues as described above with reference toFIGS. 5E-5G. That is, a silicon nitride layer 130 is deposited (FIG. 6C)and annealed to provide a receiving surface for SiO₂ and/or polysilicon.The resulting structure (analogous to that shown in FIG. 5G) isillustrated in FIG. 6D.

Based on the above recitations, it is apparent that the presentinvention may be embodied in a variety of specific forms and theforegoing disclosed embodiments are therefore to be considered in allrespects as illustrative and not restrictive. The scope of the inventionis commensurate with the claims appended hereto and is not to beotherwise limited. All variations which come within the meaning andrange of equivalency of the claims are intended to be embraced therein.

What is claimed is:
 1. An integrated circuit structure comprising:alayer comprising diamond material (96) and having a first surface; alayer of silicon nitride (98) on the first surface of the diamond layer;and a layer of device quality semiconductor material (94) suitable fordevice formation positioned over the silicon nitride layer; and abonding layer (102) between the semiconductor material layer and thesilicon nitride layer.
 2. The structure of claim 1 wherein the bondinglayer comprises at least a layer comprising silicon dioxide.
 3. Thestructure of claim 1 wherein the bonding layer includes a layercomprising silicide.
 4. The structure of claim 3 wherein the bondinglayer comprises platinum silicide.
 5. The structure of claim 1 whereinthe bonding layer comprises a layer of silicon.
 6. The structure ofclaim 1 further comprising a die attach structure bonded directly to thediamond layer.
 7. An integrated circuit structure comprising:a layercomprising diamond material and having first and second surfaces; firstand second layers of silicon nitride respectively on the first andsecond surfaces of the diamond layer; and a layer of device qualitysemiconductor material positioned over the silicon nitride layer.
 8. Anintegrated circuit structure comprising:a layer comprising diamondmaterial (96) and having a first surface; a layer of silicon nitride(98) on the first surface of the diamond layer; a layer of devicequality semiconductor material (94) positioned over the silicon nitridelayer; and a bonding layer (102) between the semiconductor materiallayer and the silicon nitride layer; wherein the layer of device qualitysemiconductor material includes a plurality of trenches (104), eachtrench defining an electronically isolated island comprising the devicequality semiconductor material.
 9. The structure of claim 8 wherein thetrenches (104) extend through the layer of semiconductor material to thediamond layer and the layer of silicon nitride is formed within thetrenches.
 10. The structure of claim 8 wherein the trenches (104) extendthrough the layer of device quality semiconductor material to thesilicon nitride layer and the silicon nitride layer continuously extendsalong lower portions of multiple trenches.
 11. The structure of claim 8wherein the device quality semiconductor material comprises amonocrystalline silicon lattice structure having an upper surface alonga 1,0,0 lattice plane; and the trenches extend into the structure along1,1,1 planes.
 12. An integrated circuit structure comprising:arelatively thick layer of diamond for supporting and insulating theintegrated circuit, said diamond being thick enough to provide integrityfor the integrated circuit without warping the integrated circuit; alayer of device quality semiconductor material positioned over thediamond layer; and a single bonding and oxide barrier layer on onesurface of the diamond layer and between the diamond layer and the layerof device quality silicon for providing an effective barrier tooxidation of said one surface of the diamond layer and for bonding thediamond layer to the device quality semiconductor layer.
 13. Theintegrated circuit of claim 12 further comprising a second oxide barrierlayer on the other surface of the diamond layer.
 14. The integratedcircuit of claim 13 wherein the second oxide barrier layer comprisessilicon nitride.
 15. The integrated circuit of claim 12 wherein thebonding and oxide barrier layer comprises silicon nitride.
 16. Theintegrated circuit of claim 12 wherein the layer of device qualitysemiconductor material includes a plurality of trenches, each trenchdefining an electronically isolated islands comprising device qualitysemiconductor material.
 17. The integrated circuit of claim 16 whereinthe bottoms of the trenches extend to the diamond layer and the bottomsof the trenches have an oxide barrier.
 18. The integrated circuit ofclaim 16 wherein the bottoms of the trenches have a layer of siliconnitride on the surface of the diamond layer.
 19. The integrated circuitof claim 12 wherein the bonding and oxide barrier layer comprisessilicon.
 20. The integrated circuit of claim 19 wherein one surface ofthe silicon bonding and oxide barrier layer on the surface of thediamond is not oxidized and the other surface of the silicon bonding andoxide barrier layer is oxide bonded to the device quality semiconductorlayer.
 21. The integrated circuit of claim 19 wherein one surface of thesilicon bonding and oxide barrier layer on the surface of the diamond isnot oxidized and the other surface of the silicon bonding and oxidebarrier layer is silicide bonded to the device quality semiconductorlayer.
 22. The integrated circuit of claim 12 further comprising a dieattach layer on the other surface of the diamond support and insulatinglayer.
 23. The integrated circuit of claim 12 wherein the bonding andoxide barrier layer further provides a carbon diffusion barrier forpreventing diffusion of carbon from the diamond layer into the devicequality semiconductor layer.
 24. The integrated circuit of claim 23wherein the bonding and oxide barrier layer comprises one materialselected from the group consisting of silicon nitride, boron nitride andaluminum nitride.